Come watch the EDA troublemakers answer the edgy, user-submitted questions about this year's most controversial issues! It's an old style open Q&A from the days before corporate marketing and paid bloggers took over every aspect of an EDA company's ... EDA Café, 1 month ago
Going to DAC? Register for the DAC'15 Troublemakers Panel - Deep Chip, 1 month ago
The Cadence and Applied Materials joint development programme is focused on front end-of-line and wafer-level CMP modelling. Applied Materials can use the Cadence CMP Process Optimiser, a tool that allows silicon calibration of semi-physical models ...Electronic Specifier, 1 week ago Cadence And Applied Materials ... EFYTimes.com, 1 week ago Cadence and Applied Materials Collaborate on Joint Development Program to Optimize Planarization Process through Advanced CMP Modeling ThomasNet, 6 days ago Cadence, Applied Materials Collaborate to Optimize CMP Process for Advanced-Node 14nm Designs Azonano, 1 week ago
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Where once the world could be split into analogue and digital, mixed signal is becoming the norm and with that comes an increasing level of complexity which chip designers have to tackle. One company that knows the problem well is Cadence Design ...Electronic Specifier, 3 weeks ago
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