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About 452 results for "vlsi"

BA20 processor IP, an alternative to ARM Cortex M
Electronics Engineering Herald

BA20 processor IP, an alternative to ARM Cortex M

VLSI processor IP vendor Cast suggests EEs a smartest processor core choice, where the core is also offered with an evaluation kit. The processor core family is BA2x Processor Family running on evaluation kit called Talos Series. The evaluation kit ... Electronics Engineering Herald, 3 days ago

19 images for vlsi

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Electronics Engineering Herald, 1 month ago
India Tech Online

Formal Verification

: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this ...
 Research and Markets2 days ago VLSI IP design platform for USB based HID  Electronics Engineering Herald3 weeks ago IOT was the central focus at a VLSI design event held in Bengaluru  Electronics Engineering Herald1 month ago VLSI design training: not "all is well"  Electronics Engineering Herald1 month ago
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India Tech Online

VLSI Conference hosts first-ever IoT Ideathon, triggers 25 innovations

: The first ever Internet of Things Ideathon ended here today with 25 innovative ideas offered to address challenges Vaccine Monitoring, Haptic Feedback for Physically Challenged and Smart Street Lighting. It was held concurrently with the 28th ...
 India Tech Online1 month ago The Fist IoT-Ideathon Kicks Off In ...  EFYTimes.com1 month ago The First IoT-Ideathon Kicks off in Bangalore Today  APN News2 months ago VLSI conference comes to Bangalore, with an Ideathon to trigger innovation  India Tech Online2 months ago

BU signs MoU for new courses

Bharathiar University on Wednesday inked an understanding with UTL Technologies to offer courses in VLSI Design, Mobile Communication and Network Security.A release from the
 The Hindu2 weeks ago BU signs MoU with UTL Technologies  Business Standard India2 weeks ago MOU - BU signs MoU with UTL Technologies  Namibia Press Agency2 weeks ago

Data compression VLSI IP cores for your chip designs

CAST is adding data compression cores sourced from its new partner Sandgate Technologies to its line of processors, peripherals, and other semiconductor IP. The ZipAccel-C Compression and ZipAccel-D Decompression IP Cores are hardware lossless ...
 Electronics Engineering Herald1 month ago

IEEE Launches First Blended Learning Program in VLSI in the Bangalore Region

Bangalore : IEEE announced the availability of the IEEE Blended Learning Program in Very Large Scale Integration (VLSI) for both corporate and academic organizations at the International Conference on VLSI Design, 2015 being held from Jan 3-7 in ...
 APN News1 month ago IEEE launches blended learning programme in VLSI  India Tech Online2 months ago
Design and Reuse

Pitfalls for Logical Equivalence Check

Preeti Agarwal, Abhishek Mahajan & Gaurav Goyal (Freescale Semiconductor) The VLSI design cycle is partitioned into two phases i.e. front-end and back-end phases of the complete SoC design cycle. While at front-end, most of the architectural ...
 Design and Reuse1 month ago

10X boost in VLSI design throughput using latest place and route from Synopsys

Date: 18/01/2015 Synopsys has recently released its 2014.12 version of new IC Compiler II place and route solution, which the company claims as game-changing successor to IC Compiler, the older place and route VLSI chip design tool from Synopsys.
 Electronics Engineering Herald1 month ago
Electronics Engineering Herald

VLSI/Semiconductor tech 2015: At 7nm Silicon giving way to Ge, III-IV, CNT and Graphene

In 1950s, when industry has moved from vacuum-tube diodes and triodes to solid-state diodes and transistors, electronic-s device researchers have selected Germanium as their semiconductor material. Early solid state diodes and bipolar junction ...
 Electronics Engineering Herald1 month ago
EE Times Europe

Monolithic 3D integration beats next node

During a 3D-VLSI workshop preceding IEDM 2014, in San Francisco, CEA-Leti presented its latest results on multi-layer transistors stacking for true 3D monolithic integration, that is without relying on tall through silicon vias (TSVs) and coarse ...
 EE Times Europe1 month ago CEA Leti presented 3D building of transistors at IEDM  Electronics Engineering Herald2 months ago Leti Will Discuss CoolCubeTM Technology For 3D Transistor Stacking At Workshop Preceding IEDM 2014  EFYTimes.com2 months ago
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