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About 620 results for "vlsi"

Bangalore startup crafts award winning remote cardiac monitor
India Tech Online

Cadence' new VLSI physical implementation tool score high in p...

Date: 15/03/2015 Cadence Design Systems said its new VLSI design physical implementation place and route EDA software tool Innovus delivers 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm node ... Electronics Engineering Herald, 1 week ago
Formal Verification Research and Markets, 3 weeks ago
VLSI IP design platform for USB based HID Electronics Engineering Herald, 1 month ago

19 images for vlsi

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EDA Café, 2 months ago
APN News, 2 months ago
Wireless Design & Development, 2 months ago
India Tech Online, 2 months ago
Electronics Engineering Herald, 2 months ago
Electronics Engineering Herald, 2 months ago

New AXI4 verification IP from eInfochips for FPGA and SoC designs

Date: 08/03/2015 India based VLSI design services company eInfochips has announced the availability of the AXI4 Verification IP (VIP) to improve reliability of FPGA and SoC designs based on the popular ARM AMBA 4 architecture. The solution already ...
 Electronics Engineering Herald2 weeks ago eInfochips Receives ARINC 429 Verification IP for Data Transfer  Rotor & Wing3 days ago eInfochips Improves Reliability for Avionics Systems With New ARINC 429 Verification IP  Franklin Credit Management Corporation4 days ago eInfochips Introduces ARINC 429 Verification IP  Individual.com1 day ago
Electronics Engineering Herald

BA20 processor IP, an alternative to ARM Cortex M

VLSI processor IP vendor Cast suggests EEs a smartest processor core choice, where the core is also offered with an evaluation kit. The processor core family is BA2x Processor Family running on evaluation kit called Talos Series. The evaluation kit ...
 Electronics Engineering Herald3 weeks ago

BU signs MoU for new courses

Bharathiar University on Wednesday inked an understanding with UTL Technologies to offer courses in VLSI Design, Mobile Communication and Network Security.A release from the
 The Hindu1 month ago BU signs MoU with UTL Technologies  Business Standard India1 month ago MOU - BU signs MoU with UTL Technologies  Namibia Press Agency1 month ago
India Tech Online

VLSI Conference hosts first-ever IoT Ideathon, triggers 25 innovations

: The first ever Internet of Things Ideathon ended here today with 25 innovative ideas offered to address challenges Vaccine Monitoring, Haptic Feedback for Physically Challenged and Smart Street Lighting. It was held concurrently with the 28th ...
 India Tech Online2 months ago The Fist IoT-Ideathon Kicks Off In ...  EFYTimes.com2 months ago The First IoT-Ideathon Kicks off in Bangalore Today  APN News2 months ago First IoT-Ideathon kicks off in Bangalore - Over a 100 participants working on 25 distinct themes will be battling it out for the next 60 hours to create the most innovative IoT products for India and the world  Cyber India Online2 months ago

Data compression VLSI IP cores for your chip designs

CAST is adding data compression cores sourced from its new partner Sandgate Technologies to its line of processors, peripherals, and other semiconductor IP. The ZipAccel-C Compression and ZipAccel-D Decompression IP Cores are hardware lossless ...
 Electronics Engineering Herald1 month ago
Design and Reuse

Pitfalls for Logical Equivalence Check

Preeti Agarwal, Abhishek Mahajan & Gaurav Goyal (Freescale Semiconductor) The VLSI design cycle is partitioned into two phases i.e. front-end and back-end phases of the complete SoC design cycle. While at front-end, most of the architectural ...
 Design and Reuse2 months ago
Electronics Engineering Herald

VLSI/Semiconductor tech 2015: At 7nm Silicon giving way to Ge, III-IV, CNT and Graphene

In 1950s, when industry has moved from vacuum-tube diodes and triodes to solid-state diodes and transistors, electronic-s device researchers have selected Germanium as their semiconductor material. Early solid state diodes and bipolar junction ...
 Electronics Engineering Herald2 months ago
EE Times Europe

Monolithic 3D integration beats next node

During a 3D-VLSI workshop preceding IEDM 2014, in San Francisco, CEA-Leti presented its latest results on multi-layer transistors stacking for true 3D monolithic integration, that is without relying on tall through silicon vias (TSVs) and coarse ...
 EE Times Europe2 months ago

IEEE Launches First Blended Learning Program in VLSI in the Bangalore Region

Bangalore : IEEE announced the availability of the IEEE Blended Learning Program in Very Large Scale Integration (VLSI) for both corporate and academic organizations at the International Conference on VLSI Design, 2015 being held from Jan 3-7 in ...
 APN News2 months ago
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